This FPGA tutorial will guide you how to control the 4-digit seven-segment display on Basys 3 FPGA Board. A display controller will be designed in Verilog for displaying numbers on the 4-digit 7-segment LED display of the Basys 3 FPGA. Full Verilog code for the seven-segment LED display controller will also be provided.
The Basys 3 FPGA has a common-anode 4-digit 7-segment LED display as shown in the following figure.
Last time, I presented a Verilog code together with Testbench for Sequence Detector using FSM. The sequence being detected was "1011".
This VHDL project presents a full VHDL code for Moore FSM Sequence Detector. A VHDL Testbench is also provided for simulation. The sequence to be detected is "1001".
This Verilog project is to present a full Verilog code for Sequence Detector using Moore FSM. A Verilog Testbench for the Moore FSM sequence detector is also provided for simulation.
The Moore FSM keeps detecting a binary sequence from a digital input and the output of the FSM goes high only when a "1011" sequence is detected. The state diagram of the Moore FSM for the sequence detector is shown in the following figure.
Last time, I presented a Verilog code for a 16-bit single-cycle MIPS processor. The instruction set and architecture design for the MIPS processor was provided here.
Today, the VHDL code for the MIPS Processor will be presented. A simple VHDL testbench for the MIPS processor will be also provided for simulation purposes.
This VHDL project presents a car parking system in VHDL using Finite State Machine (FSM). VHDL code and testbench for the car parking system are fully provided.
The VHDL car parking system is shown in the following figure. There is a front sensor to detect vehicles going to the gate of the car parking system. Another back sensor is to detect if the coming vehicle passed the gate and getting into the car park.
