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16-bit ALU Design in VHDL using Verilog N-bit Adder

Last time, I introduced the N-bit adder design in Verilog, which is a part of a 16-bit ALU design I will present today. The 16-bit ALU is a core combinational component of the processing unit in the coprocessor I introduced in the previous post.

Full VHDL code for 16-bit ALU together with testbench will be presented in this VHDL project. 

VHDL code for 16-bit ALU

N-bit Adder Design in Verilog

The next Verilog/ VHDL project is a complete co-processor specially designed for cryptographic applications. The co-processor has standard instructions and dedicated function units specific for security. The co-processor is implemented mainly in VHDL, but the N-bit Adder is designed in Verilog. The Verilog code for the N-bit Adder will be instantiated later in a VHDL design. In next posts, implementations of major modules in the co-processor will be presented. The complete co-processor design and implementation will be presented after every part of the co-processor is posted.

This post presents Verilog code for N-bit Adder designed for the co-processor. The Verilog code for N-bit Adder is done by using Structural Modeling. 

Verilog code for N-bit Adder using Structural modeling

Verilog code for Multiplexers

Multiplexers are one of the main combinational logic components in digital circuits. Multiplexers are used for selecting one of many different digital inputs and forwarding to the output based on the controlling signals. 

In this Verilog project, Verilog code for multiplexers such as 2-to-1 multiplexer, 2x5-to-5 multiplexer and 2x32-to-32 multiplexer are presented. 

Verilog code for multiplexer