VHDL code for debouncing buttons on FPGA

When pressing buttons on FPGA, there are unpredictable bounces which are unwanted. This VHDL code is to debounce buttons on FPGA by only generating a single pulse with a period of the input clock when the button on FPGA is pressed, held long enough, and released. Last time, I presented a simple Verilog code for debouncing buttons on FPGA.

This VHDL project is to present a VHDL code for debouncing buttons on FPGA. Full VHDL code and testbench are provided.

VHDL code for debouncing buttons on FPGA

How to generate a clock enable signal instead of creating another clock domain

This post is about to tell you how to generate a clock enable signal (not gated clocks) to drive another logic using the same clock domain instead of creating another clock domain (using clock dividers) causing timing issues or clock domain crossing problems such as metastability, data loss, and data incoherency. 
How to generate a clock enable signal instead of creating another clock domain

The multi-clock domain crossing problem is very common in digital logic design. When you interface signals between different clock domains, metastability and data loss/incoherency are likely to happen. The most popular way to prevent this is using multi-Flip-Flop synchronizers to synchronize the input signals from another clock domain. 

To avoid the clock domain crossing issue, it is better to generate a slow clock enable signal instead of creating another slower clock (using clock dividers) to drive another logic part of your design. 

For example, in your FPGA, there is a 50MHz clock available, but you want to drive another part of your design using a slower clock of 1KHz. Instead of creating another clock of 1KHz, you should create a 1KHz clock enable signal. 

Below is an example VHDL code for generating the slow clock enable signal:

-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects,
-- Generate clock enable signal instead of creating another clock domain
-- Assume that the input clock : clk_50MHz
signal clock_1KHz_enable  : std_logic;
signal counter : std_logic_vector(15 downto 0):=x"0000";
constant DIVISOR: std_logic_vector(15 downto 0):= x"C34F";
-- Generate the slow enable signal instead of creating another clock of 1KHz
-- 
process(clk_50MHz)
begin
  if(rising_edge(clk_50MHz)) then
    if(counter = DIVISOR) then
      counter <= x"0000";
      clock_1KHz_enable <= '1';
    else
      clock_1KHz_enable <= '0';
      counter <= counter + x"0001";
    end if;
  end if;
end process;
-- Use the same clock and the slow clock enable signal above 
-- to drive another part of the design to avoid domain crossing issues
process(clk_50MHz)
begin
  if(rising_edge(clk_50MHz)) then
    if(clock_1KHz_enable = '1') then
      -- Add your logic here
      -- It will be executed like a process of 1Khz clock
    end if;
  end if;
end process;
By creating the clock enable signal instead, all the logic in your design are driven by the same clock domain so that you won't need to worry about the multi-clock domain crossing problems. You can change the DIVISOR constant value to get any clock enable frequency that you want. Another Verilog example code for generating a slow clock enable signal instead of creating another clock domain: here.
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Verilog code for Clock divider on FPGA

Last time, I presented a VHDL code for a clock divider on FPGA. This Verilog project provides full Verilog code for the Clock Divider on FPGA together with Testbench for simulation. The Verilog clock divider is simulated and verified on FPGA.

Verilog code for Clock divider on FPGA

VHDL Code for Clock Divider on FPGA

This VHDL project presents a full VHDL code for clock divider on FPGA. Testbench VHDL code for clock divider is also provided. The VHDL code for the clock divider is synthesizable and verified on FPGA.

VHDL Code for Clock Divider on FPGA

Verilog vs VHDL: Explain by Examples

Last time, I presented in detail what actually FPGA programming is and how to get started with FPGA design. A brief history of Verilog and VHDL was also discussed. If you search for the difference between Verilog and VHDL, you will see many difference pages discussing this HDL language war, but most of them are short and not well-explained by examples for facilitating beginners or students' understanding.

The difference between Verilog and VHDL will be explained in detail by examples in this post. The advantages and disadvantages of Verilog and VHDL will be also discussed.

Verilog vs VHDL: Explain by Example

What is FPGA Programming?

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Today, I will present what actually FPGA programming is, how to get started with FPGA programming, and FPGA programming design flow. The difference between FPGA programming and software programming will be also discussed.

What is FPGA Programming?