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Saturday, June 24, 2017

Verilog code for Arithmetic Logic Unit (ALU)

Last time, an Arithmetic Logic Unit (ALU) is designed and implemented in VHDL. Full VHDL code for the ALU was presented. 

Today, fpga4student presents the Verilog code for the ALU. The testbench Verilog code for the ALU is also provided for simulation.


Verilog code for ALU

Saturday, June 17, 2017

VHDL code for Arithmetic Logic Unit (ALU)

Arithmetic Logic Unit (ALU) is one of the most important digital logic components in CPUs. It normally executes logic and arithmetic operations such as addition, subtraction, multiplication, division, etc.

In this VHDL project, an ALU is designed and implemented in VHDL. VHDL code for the ALU is fully presented.

VHDL code for ALU

Saturday, June 10, 2017

Tic Tac Toe Game in Verilog and LogiSim

Tic Tac Toe is a very popular paper-and-pencil game in a 3x3 grid for two players. The player who makes the first three of their marks in a diagonal, vertical, or horizontal row wins the game.

Today, fpga4student designs and implements the Tic Tac Toe game in Verilog and Logisim. 

Tic Tac Toe Game in Verilog and LogiSim

Tuesday, June 6, 2017

PWM Generator in VHDL with Variable Duty Cycle

Pulse Width Modulation (PWM) is a very popular modulation technique which is mainly used to control the power delivered to electrical devices such as motors.

This post presents a simple VHDL code for PWM Generator with Variable Duty Cycle. The VHDL code for PWM Generator is simulated and verified on Xilinx ISIM.

VHDL code for PWM Generator

VHDL code for PWM Generator with Variable Duty Cycle:

-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects 
-- VHDL code for PWM Generator 
-- Two de-bounced push-buttons
-- One: increase duty cycle by 10%
-- Another: Decrease duty cycle by 10%
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
entity PWM_Generator is
port (
   clk: in std_logic; -- 100MHz clock input 
   DUTY_INCREASE: in std_logic; -- button to increase duty cycle by 10%
   DUTY_DECREASE: in std_logic; -- button to decrease duty cycle by 10%
   PWM_OUT: out std_logic -- PWM signal out with frequency of 10MHz
  );
end PWM_Generator;

architecture Behavioral of PWM_Generator is
 -- D-Flip-Flop for debouncing module
 component DFF_Debounce 
 Port ( 
  CLK : in std_logic;
  D : in std_logic;
  Q : out std_logic
  );
 end component;
 signal slow_clk: std_logic:='0'; -- slow clock for deboucing
 signal counter_slow: std_logic_vector(27 downto 0):=(others => '0');-- counter for creating slow clock
 signal tmp1,tmp2,duty_inc: std_logic;-- temporary signals for deboucing
 signal tmp3,tmp4,duty_dec: std_logic;-- temporary signals for deboucing
 signal counter_PWM: std_logic_vector(3 downto 0):=(others => '0');-- counter for PWM signal
 signal DUTY_CYCLE: std_logic_vector(3 downto 0):=x"5";
begin
 -- Debouncing process
 -- First generate slow clock for deboucing (4Hz)
 process(clk)
 begin
  if(rising_edge(clk)) then
   counter_slow <= counter_slow + x"0000001";
   --if(counter_slow>=x"17D7840") then -- for running on FPGA -- comment when running simulation
   if(counter_slow>=x"0000001") then -- for running simulation -- comment when running on FPGA
    counter_slow <= x"0000000";
   end if;
  end if;
 end process;
 --slow_clk <= '0' when counter_slow < x"0BEBC20" else '1';-- for running on FPGA -- comment when running simulation
 slow_clk <= '0' when counter_slow < x"000001" else '1';-- for running simulation -- comment when running on FPGA
 -- debounce part for duty increasing button
 stage0: DFF_Debounce port map(clk, DUTY_INCREASE, tmp1);
 stage1: DFF_Debounce port map(clk, tmp1, tmp2); 
 duty_inc <=  tmp1 and (not tmp2);
 -- debounce part for duty decreasing button
 stage2: DFF_Debounce port map(clk, DUTY_DECREASE, tmp3);
 stage3: DFF_Debounce port map(clk, tmp3, tmp4); 
 duty_dec <=  tmp3 and (not tmp4);
 -- for controlling duty cycle by these buttons
 process(slow_clk)
 begin
  if(rising_edge(slow_clk)) then
   if(duty_inc='1' and DUTY_CYCLE <= x"9") then
    DUTY_CYCLE <= DUTY_CYCLE + x"1";--increase duty cycle by 10%
   elsif(duty_dec='1' and DUTY_CYCLE>=x"1") then
    DUTY_CYCLE <= DUTY_CYCLE - x"1";--decrease duty cycle by 10%
   end if;
  end if;
 end process;
 -- Create 10MHz PWM signal
 process(clk)
 begin
  if(rising_edge(clk)) then
   counter_PWM <= counter_PWM + x"1";
   if(counter_PWM>=x"9") then
    counter_PWM <= x"0";
   end if;
  end if;
 end process;
 PWM_OUT <= '1' when counter_PWM < DUTY_CYCLE else '0';
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects 
-- VHDL code for D Flip Flop
-- D-Flip-Flop for debouncing module
entity DFF_Debounce is
Port ( 
 CLK : in std_logic;
 D : in std_logic;
 Q : out std_logic
 );
end DFF_Debounce;
architecture Behavioral of DFF_Debounce is
begin
process(CLK)
begin
 if (rising_edge(CLK)) then
  Q <= D;
 end if;
end process;
end Behavioral;

VHDL Testbench code for the PWM Generator with Variable Duty Cycle:

-- fpga4student.com: FPGA Projects, Verilog projects, VHDL projects 
-- VHDL testbench code for PWM Generator 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_PWM_Genenrator IS
END tb_PWM_Genenrator;
 
ARCHITECTURE behavior OF tb_PWM_Genenrator IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT PWM_Generator
    PORT(
         clk : IN  std_logic;
         DUTY_INCREASE : IN  std_logic;
         DUTY_DECREASE : IN  std_logic;
         PWM_OUT : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal DUTY_INCREASE : std_logic := '0';
   signal DUTY_DECREASE : std_logic := '0';

  --Outputs
   signal PWM_OUT : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
 -- Instantiate the Unit Under Test (UUT)
   uut: PWM_Generator PORT MAP (
          clk => clk,
          DUTY_INCREASE => DUTY_INCREASE,
          DUTY_DECREASE => DUTY_DECREASE,
          PWM_OUT => PWM_OUT
        );

   -- Clock process definitions
   clk_process :process
   begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin  
  DUTY_INCREASE <= '0';
  DUTY_DECREASE <= '0';
      wait for clk_period*10; 
  DUTY_INCREASE <= '1'; 
      wait for clk_period*10;
  DUTY_INCREASE <= '0';
      wait for clk_period*10; 
  DUTY_INCREASE <= '1';
      wait for clk_period*10;
  DUTY_INCREASE <= '0';
      wait for clk_period*10; 
  DUTY_INCREASE <= '1';
      wait for clk_period*10;
  DUTY_INCREASE <= '0';
      wait for clk_period*10; 
  DUTY_DECREASE <= '1'; 
      wait for clk_period*10;
  DUTY_DECREASE <= '0';
      wait for clk_period*10; 
  DUTY_DECREASE <= '1';
      wait for clk_period*10;
  DUTY_DECREASE <= '0';
      wait for clk_period*10; 
  DUTY_DECREASE <= '1';
      wait for clk_period*10;
  DUTY_DECREASE <= '0';
      wait for clk_period*10;  
  
      -- insert stimulus here 

      wait;
   end process;

END;

Simulation results for the PWM Generator in VHDL:

VHDL code for PWM Generator

Thursday, May 4, 2017

How to write Verilog Testbench for bidirectional/ inout ports

This post describes how to write a Verilog testbench for bidirectional or inout ports. This happens in special designs which contain bidirectional or inout ports such as I2C core, IO pads, memories, etc. 

In this post, I will give an example how to write testbench code for a digital IO pad. Basically, the IO pad has logic inputs DS, OEN, IE, PE to configure the IO pad as an input or output. When DS = OEN = IE = PE = 1, the IO pad operates as an input pad. Thus, the data from the bidirectional port PAD are written into the output C. When DS = PE =1 and OEN = IE = 0, the IO pad operates as an output pad. Therefore, the signal from the input I is passed to the bidirectional port PAD.
Verilog testbench for bidirectional/ inout port

Saturday, April 29, 2017

Simple Verilog code for debouncing buttons on FPGA

This post is to present a simple debouncing Verilog code for buttons on FPGA. Mechanical switches/ buttons cause the unpredictable bounce in the signal when toggled. There are various ways to implement debouncing circuits for buttons on FPGA. In this project, a simple debouncing circuit is implemented in Verilog to generate only a single pulse when pressing a button on FPGA

Verilog code for button debouncing

Debouncing Circuit for buttons on FPGA

Wednesday, April 12, 2017

Verilog Code for 16-bit RISC Processor

In this project, Verilog code for a 16-bit RISC processor is presented. The RISC processor is designed based on its instruction set and Harvard-type data path structure. Then, the RISC processor is implemented in Verilog and verified using Xilinx ISIM.

Verilog code for RISC processor

Sunday, March 19, 2017

Verilog code for counter with testbench

In this project, Verilog code for counters with testbench will be presented including up counter, down counter, up-down counter, and random counter.

Verilog code for counter with testbench

Wednesday, February 15, 2017

VHDL code for Full Adder

In this VHDL project, VHDL code for full adder is presented. VHDL code for the adder is implemented by using behavioral and structural models. 

The full adder has three inputs X1, X2, Carry-In Cin and two outputs S, Carry-Out Cout as shown in the following figure:
VHDL code for full adder

Saturday, February 4, 2017

Verilog code for Full Adder

In this Verilog project, Verilog code for Full Adder is presented. Both behavioral and structural Verilog code for Full Adder is implemented. 

Verilog code for Full Adder

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