fpga4student.com FPGA digital design projects using Verilog/ VHDL

Saturday, April 29, 2017

Simple debouncing Verilog code for buttons on FPGA

This post is to present a simple debouncing Verilog code for buttons on FPGA. Mechanical switches/ buttons cause the unpredictable bounce in the signal when toggled. There are various ways to implement debouncing circuits for buttons on FPGA. In this project, a simple debouncing circuit is implemented in Verilog to generate only a single pulse when pressing a button on FPGA

Verilog code for button debouncing

Debouncing Circuit for buttons on FPGA

Wednesday, April 12, 2017

Verilog Code for 16-bit RISC Processor

In this project, Verilog code for a 16-bit RISC processor is presented. The RISC processor is designed based on its instruction set and Harvard-type data path structure. Then, the RISC processor is implemented in Verilog and verified using Xilinx ISIM.

Verilog code for RISC processor

Sunday, March 19, 2017

Verilog code for counter with testbench

In this project, Verilog code for counters with testbench will be presented including up counter, down counter, up-down counter, and random counter.

Verilog code for counter with testbench

Wednesday, February 15, 2017

VHDL code for Full Adder

In this VHDL project, VHDL code for full adder is presented. VHDL code for the adder is implemented by using behavioral and structural models. 

The full adder has three inputs X1, X2, Carry-In Cin and two outputs S, Carry-Out Cout as shown in the following figure:
VHDL code for full adder

Saturday, February 4, 2017

Verilog code for Full Adder

In this Verilog project, Verilog code for Full Adder is presented. Both behavioral and structural Verilog code for Full Adder is implemented. 

Verilog code for Full Adder

Friday, February 3, 2017

VHDL code for D Flip Flop

  VHDL code for D Flip Flop is presented in this project. Verilog code for D Flip Flop here. There are several types of D Flip Flops such as high-level asynchronous reset D Flip-Flop, low-level asynchronous reset D Flip-Flop, synchronous reset D-Flip-Flop, rising edge D Flip-Flop, falling edge D Flip-Flop, which is implemented in VHDL in this project.

VHDL code for D Flip Flop

Verilog code for a comparator

In this project, a simple 2-bit comparator is designed and implemented in Verilog HDL. Truth table, K-Map and minimized equations for the comparator are presented. The Verilog code of the comparator is simulated by ModelSim and the simulation waveform is presented.
Verilog code for a comparator

Verilog code for D Flip Flop

D Flip-Flop is a fundamental component in digital logic circuits. Verilog code for D Flip Flop is presented in this project. There are two types of D Flip-Flops being implemented which are Rising-Edge D Flip Flop and Falling-Edge D Flip Flop. 

Verilog code for D Flip Flop

Sunday, January 29, 2017

VHDL code for FIFO Memory

     As requested by some readers, I made the VHDL code for the FIFO memory in this post(Verilog code for FIFO memory). 

The FIFO has 16 8-bit data-width stages and five status signals including overflow, underflow, empty, full and threshold. The VHDL code for the FIFO memory is verified by the same Verilog testbench code by doing a mixed language simulation on Xilinx ISIM. 
VHDL code for FIFO Memory

Friday, January 27, 2017

Verilog code for FIFO memory

  In this project, Verilog code for FIFO memory is presented. 

The First-In-First-Out (FIFO) memory with the following specification is implemented in Verilog:
  • 16 stages
  • 8-bit data width 
  • Status signals: 
    • Full: high when FIFO is full else low.
    • Empty: high when FIFO is empty else low.
    • Overflow: high when FIFO is full and still writing data into FIFO, else low.
    • Underflow: high when FIFO is empty and still reading data from FIFO, else low.
    • Threshold: high when the number of data in FIFO is less than a specific threshold, else low.

Verilog code for FIFO memory

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