Wednesday, April 12, 2017
Sunday, March 19, 2017
Wednesday, February 15, 2017
Saturday, February 4, 2017
Friday, February 3, 2017
VHDL code for D Flip Flop is presented in this project. Verilog code for D Flip Flop here. There are several types of D Flip Flops such as high-level asynchronous reset D Flip-Flop, low-level asynchronous reset D Flip-Flop, synchronous reset D-Flip-Flop, rising edge D Flip-Flop, falling edge D Flip-Flop, which is implemented in VHDL in this project.
Sunday, January 29, 2017
As requested by some readers, I made the VHDL code for the FIFO memory in this post(Verilog code for FIFO memory).
The FIFO has 16 8-bit data-width stages and five status signals including overflow, underflow, empty, full and threshold. The VHDL code for the FIFO memory is verified by the same Verilog testbench code by doing a mixed language simulation on Xilinx ISIM.
Friday, January 27, 2017
In this project, Verilog code for FIFO memory is presented.
The First-In-First-Out (FIFO) memory with the following specification is implemented in Verilog:
- 16 stages
- 8-bit data width
- Status signals:
- Full: high when FIFO is full else low.
- Empty: high when FIFO is empty else low.
- Overflow: high when FIFO is full and still writing data into FIFO, else low.
- Underflow: high when FIFO is empty and still reading data from FIFO, else low.
- Threshold: high when the number of data in FIFO is less than a specific threshold, else low.
Wednesday, January 25, 2017
In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor, which is widely used by many universities in academic courses related to computer organization and architecture.
The Instruction Format and Instruction Set Architecture for the 16-bit single-cycle MIPS are as follows:
|Instruction set for the MIPS processor|