fpga4student.com FPGA digital design projects using Verilog/ VHDL: Verilog Implementation of Plate License Recognition on FPGA

Monday, December 5, 2016

Verilog Implementation of Plate License Recognition on FPGA

      A plate license recognition system is implemented in Matlab and then it is implemented on FPGA Xilinx Spartan-6 using Verilog. Below is the test environment for the system on FPGA.

Verilog code for License Plate Recognition


Image memory: 10 images and convert it into .dat format ( gray data). We use $readmemh(synthesizable) Verilog command to initialize the memory by reading gray data from .dat file. 10 images are converted into Gray format and write to the .dat file by using Matlab.


Plate License Recognition core: Use a switch on FPGA as the “start” signal to trigger this core working and output the plate license numbers.

Monitor on LEDs: When the “done” signal is rising-edge, this block periodically displays plate license numbers.  

Verilog code for License Plate Recognition

Top level Verilog code:

 module Test_top(input clk // 33MHz   
                               ,rst, start,  
                               output reg[5:0] led  
   );  
      reg [7:0] image_pixel_val;  
      // Outputs  
      wire done;  // fpga4student.com FPGA projects, Verilog projects, VHDL projects 
      wire [15:0] image_pixel_addr;  
      wire [5:0] ReadCh;  
      reg[5:0] num1,num2,num3,num4,num5,num6,num7;  
      reg [2:0] count,count_4s;  
      wire CharCheck;  
      reg clk_4s,display;  
      integer counter;  
      reg [7:0] image_inv [0:65535];  
      LPChRec uut (  
           .clk(clk),   
           .rst(rst),   
           .start(start),  
           .image_pixel_val(image_pixel_val),  
           .image_pixel_addr(image_pixel_addr),  
           .ReadCh(ReadCh),   
           .CharCheck(CharCheck),  
           .done(done)  
      );  
      initial begin  
      $readmemh ("10.dat", image_inv, 0, 65535);  
      end  
      always @(posedge clk or posedge rst) // clock 4s  
      begin  
           if(rst) begin  
                clk_4s <= 1'b0;  
                counter <= 0;  
                end  
           else  
           begin  
                counter <= counter + 1;  
                if(counter <= 66000000) clk_4s <= 1'b0;  
                else if(counter > 132000000)   
                begin  
                     counter <=0;  
                end  
                else  
                clk_4s <= 1'b1;  
           end  
      end  
      always @(posedge clk)  
      begin  
           image_pixel_val <= image_inv[image_pixel_addr];            
      end  
// fpga4student.com FPGA projects, Verilog projects, VHDL projects 
   always @(posedge clk or posedge rst)  
      begin  
           if(rst) begin   
                count = 3'd0;  
                num1 <= 40;  
                num2 <=0;  
                num3 <= 0;  
                num4 <= 0;  
                num5 <= 0;  
                num6 <= 0;  
                display <= 0;  
                end  
           else  
           begin  
                if(CharCheck) begin  
                count = count + 1'd1;  
                if(count==3'd1)   
                     num1 <= ReadCh;  
                else if(count==3'd2)  
                     num2 <= ReadCh;  
                else if(count==3'd3)  
                     num3 <= ReadCh;  
                else if(count==3'd4)  
                     num4 <= ReadCh;  
                else if(count==3'd5)  
                     num5 <= ReadCh;  
                else if(count==3'd6)  
                     num6 <= ReadCh;  
                else if(count==3'd7)  
                     num7 <= ReadCh;  
                else begin  
                num1 <= 0;  
                num2 <=0;  
                num3 <= 0;  
                num4 <= 0;  
                num5 <= 0;  
                num6 <= 0;  
                end  
                end  
                if(done) display <= 1;  
           end  
      end  
// fpga4student.com FPGA projects, Verilog projects, VHDL projects 
      always @(posedge clk_4s or posedge rst) begin  
           if(rst) begin count_4s <= 0; led <=0; end  
           else begin   
           if(display) begin  
           count_4s <= count_4s + 1;  
           if(count_4s==0) led <= num1;  
           else if(count_4s==1) led <=num2;  
           else if(count_4s==2) led <=num3;  
           else if(count_4s==3) led <=num4;  
           else if(count_4s==4) led <=num5;  
           else if(count_4s==5) led <=num6;  
           else if(count_4s==6) led <=num7;  
           else count_4s <= 0;  
           end  
           end   
      end  
 endmodule  

 module LPChRec(  
   input clk,  // fpga4student.com FPGA projects, Verilog projects, VHDL projects 
   input rst,  
   input start,  
       input [7:0] image_pixel_val,  
       output [15:0] image_pixel_addr,  
   output [5:0] ReadCh,  
       output CharCheck,  
   output done  
   );  
 wire [7:0] ccl_th_low;  
 wire [7:0] ccl_th_high;  
 wire [7:0] image_pixel_val1;  
 wire [15:0] image_pixel_addr1;  
 wire [15:0] ImgAddr;  
 wire [7:0] ImgVal;  
 wire [7:0] ObjAddr1;  
 wire [55:0] ObjInfo;  
 wire                ccl_done,active;  
 assign ccl_th_low = 8'd40;  
 assign ccl_th_high = 8'd255;  
 assign image_pixel_addr = (active)?ImgAddr:image_pixel_addr1;  
 assign image_pixel_val1 = image_pixel_val;  
 assign ImgVal                    = image_pixel_val;  
// fpga4student.com FPGA projects, Verilog projects, VHDL projects 
 image_processor image_processor_inst (  
   .image_pixel_addr(image_pixel_addr1),   
   .image_pixel_val(image_pixel_val1),   
   .clk(clk),   
   .rst(rst),   
   .ccl_start(start),   
   .ccl_th_low(ccl_th_low),   
   .ccl_th_high(ccl_th_high),   
   .ccl_done(ccl_done),  
       .ccl_mem_result_addr(ObjAddr1),  
       .ccl_mem_result_data(ObjInfo)  
   );  
// fpga4student.com FPGA projects, Verilog projects, VHDL projects 
 CreateObj CreateObjInst (  
   .clk(clk),   
   .rst(rst),   
   .start(ccl_done),   
   .thresh(ccl_th_low),   
   .ObjInfo(ObjInfo),   
   .ImgVal(ImgVal),   
   .ObjAddr1(ObjAddr1),   
   .ImgAddr(ImgAddr),  
       .Char(ReadCh),  
       .CharCheck(CharCheck),  
   .active(active),   
   .done(done)  
   );  
 endmodule  

Verilog Testbench:

 module Test_top(input clk // 33MHz   
                               ,rst, start,  
                               output reg[5:0] led  
   );  
      reg [7:0] image_pixel_val;  
      // Outputs  
      wire done;  // fpga4student.com FPGA projects, Verilog projects, VHDL projects 
      wire [15:0] image_pixel_addr;  
      wire [5:0] ReadCh;  
      reg[5:0] num1,num2,num3,num4,num5,num6,num7;  
      reg [2:0] count,count_4s;  
      wire CharCheck;  
      reg clk_4s,display;  
      integer counter;  
      reg [7:0] image_inv [0:65535];  
      LPChRec uut (  
           .clk(clk),   
           .rst(rst),   
           .start(start),  
           .image_pixel_val(image_pixel_val),  
           .image_pixel_addr(image_pixel_addr),  
           .ReadCh(ReadCh),   
           .CharCheck(CharCheck),  
           .done(done)  
      );  
      initial begin  
      $readmemh ("10.dat", image_inv, 0, 65535);  
      end  
      always @(posedge clk or posedge rst) // clock 4s  
      begin  
           if(rst) begin  
                clk_4s <= 1'b0;  
                counter <= 0;  
                end  
           else  
           begin  
                counter <= counter + 1;  
                if(counter <= 66000000) clk_4s <= 1'b0;  
                else if(counter > 132000000)   
                begin  
                     counter <=0;  
                end  
                else  
                clk_4s <= 1'b1;  
           end  
      end  
      always @(posedge clk)  
      begin  
           image_pixel_val <= image_inv[image_pixel_addr];            
      end  
// fpga4student.com FPGA projects, Verilog projects, VHDL projects 
   always @(posedge clk or posedge rst)  
      begin  
           if(rst) begin   
                count = 3'd0;  
                num1 <= 40;  
                num2 <=0;  
                num3 <= 0;  
                num4 <= 0;  
                num5 <= 0;  
                num6 <= 0;  
                display <= 0;  
                end  
           else  
           begin  
                if(CharCheck) begin  
                count = count + 1'd1;  
                if(count==3'd1)   
                     num1 <= ReadCh;  
                else if(count==3'd2)  
                     num2 <= ReadCh;  
                else if(count==3'd3)  
                     num3 <= ReadCh;  
                else if(count==3'd4)  
                     num4 <= ReadCh;  
                else if(count==3'd5)  
                     num5 <= ReadCh;  
                else if(count==3'd6)  
                     num6 <= ReadCh;  
                else if(count==3'd7)  
                     num7 <= ReadCh;  
                else begin  
                num1 <= 0;  
                num2 <=0;  
                num3 <= 0;  
                num4 <= 0;  
                num5 <= 0;  
                num6 <= 0;  
                end  
                end  
                if(done) display <= 1;  
           end  
      end  
// fpga4student.com FPGA projects, Verilog projects, VHDL projects 
      always @(posedge clk_4s or posedge rst) begin  
           if(rst) begin count_4s <= 0; led <=0; end  
           else begin   
           if(display) begin  
           count_4s <= count_4s + 1;  
           if(count_4s==0) led <= num1;  
           else if(count_4s==1) led <=num2;  
           else if(count_4s==2) led <=num3;  
           else if(count_4s==3) led <=num4;  
           else if(count_4s==4) led <=num5;  
           else if(count_4s==5) led <=num6;  
           else if(count_4s==6) led <=num7;  
           else count_4s <= 0;  
           end  
           end   
      end  
 endmodule  

Results:
Verilog code for License Plate Recognition

Video Demo:

If you are interested, please contact via email or comment your email below
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16 comments:

  1. Hello,
    I am interested in replicating this FPGA project and was wondering if you can provide some code and documentation that I can use. Thank you for your time it is very much appreciated.

    thanks,

    Roger C.

    ReplyDelete
    Replies
    1. Please contact me through my email: loi09dt1@gmail.com

      Delete
    2. I am doing this same project for final year.Can u plz provide me the code and steps for implementing it.
      Thank you in advance

      Delete
    3. Kindly email me via admin@fpga4student.com

      Delete
  2. Thanks. Please keep update the blog: https://fpga4student.blogspot.com

    ReplyDelete
  3. Can you provide Verilog code a FSM ?

    ReplyDelete
    Replies
    1. Please refer to below links: http://www.fpga4student.com/2016/11/verilog-code-for-traffic-light-system.html
      or http://www.fpga4student.com/2016/11/verilog-code-for-parking-system-using.html
      Verilog code for Finite State Machine (FSM)

      Delete
  4. Do we need any separate program for character recognition and Detection?

    ReplyDelete
  5. We need many more others code for recognition. Not only the code above.

    ReplyDelete
  6. Do you have all the codes to implement this on fpga?If yes,can you tell me how to get it?

    ReplyDelete
    Replies
    1. Full Verilog and matlab code available. Email me: admin@fpga4student.com

      Delete
  7. does anyone have the complete code for this project? will the above code work for the number plate recognition project?

    ReplyDelete
    Replies
    1. Full Verilog and matlab code available. Email me: admin@fpga4student.com

      Delete
  8. #Tutorials, #Video, and #SourceCode (Check Description of YouTube Videos)
    #ImageProcessing #Xilinx #FPGAs #MATLAB, #VHDL
    #Vivado, #SystemGenerator, #Simulink, #HDLCoder
    #ImageProcessingOnFPGA
    #ImageProcessingUsingVHDL #ImageProcessingOnSystemGenerator
    #RealTimeCameraInterfaceWithFPGA
    https://www.youtube.com/c/dontscratchyourheadaskus/playlists

    ReplyDelete

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