### In this project, a simple 2-bit comparator is designed and implemented in Verilog HDL. Truth table, K-Map and minimized equations for the comparator are presented. The Verilog code of the comparator is simulated by ModelSim and the simulation waveform is presented.

**The specification of the 2-bit comparator is as follows:**

**Input: 2-bit A and B for comparison****Output:****A_greater_B: high if A > B else low****A_equal_B: high if A = B else low****A_less_B: high if A<B else low**

**The truth table for the comparator:**

A1 | A0 | B1 | B0 | A_greater_B | A_equal_B | A_less_B |

0 | 0 | 0 | 0 | 0 | 1 | 0 |

0 | 0 | 0 | 1 | 0 | 0 | 1 |

0 | 0 | 1 | 0 | 0 | 0 | 1 |

0 | 0 | 1 | 1 | 0 | 0 | 1 |

0 | 1 | 0 | 0 | 1 | 0 | 0 |

0 | 1 | 0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 0 | 0 | 1 |

0 | 1 | 1 | 1 | 0 | 0 | 1 |

1 | 0 | 0 | 0 | 1 | 0 | 0 |

1 | 0 | 0 | 1 | 1 | 0 | 0 |

1 | 0 | 1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 1 | 0 | 0 | 1 |

1 | 1 | 0 | 0 | 1 | 0 | 0 |

1 | 1 | 0 | 1 | 1 | 0 | 0 |

1 | 1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 1 | 0 |

**K-Map tables and the corresponding equations for the comparator:**

A_greater_B | A1A0 00 | 01 | 11 | 10 |

B1B0 00 | 0 | 1 | 1 | 1 |

01 | 0 | 0 | 1 | 1 |

11 | 0 | 0 | 0 | 0 |

10 | 0 | 0 | 1 | 0 |

**A_greater_B = B0 B1 A0 + B1 A1 + A1 A0 B0**

**= A0 B0 (B1 + A1) + + B1 A1**

A_equal_B | A1A0 00 | 01 | 11 | 10 |

B1B0 00 | 1 | 0 | 0 | 0 |

01 | 0 | 1 | 0 | 0 |

11 | 0 | 0 | 1 | 0 |

10 | 0 | 0 | 0 | 1 |

**A_equal_B = (B1 A1+A1 B1) (B0 A0+A0 B0)**

A_less_B | A1A0 00 | 01 | 11 | 10 |

B1B0 00 | 0 | 0 | 0 | 0 |

01 | 1 | 0 | 0 | 0 |

11 | 1 | 1 | 0 | 1 |

10 | 1 | 1 | 0 | 0 |

**A_less_B = A0 A1 B0 + A1 B1 + B1 B0 A0**

**After obtaining the minimized equations of the outputs of the comparator, it is easy to write Verilog code for the comparator.**

####
**Below is the Verilog code for the comparator:**

```
// FPGA projects using Verilog/ VHDL
// fpga4student.com : FPGA projects, Verilog projects, VHDL projects
// Verilog code for 2-bit comparator
module comparator(input [1:0] A,B, output A_less_B, A_equal_B, A_greater_B);
wire tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8;
// A = B output
xnor u1(tmp1,A[1],B[1]);
xnor u2(tmp2,A[0],B[0]);
and u3(A_equal_B,tmp1,tmp2);
// A less than B output
assign tmp3 = (~A[0])& (~A[1])& B[0];
assign tmp4 = (~A[1])& B[1];
assign tmp5 = (~A[0])& B[1]& B[0];
assign A_less_B = tmp3 | tmp4 | tmp5;
// A greater than B output
assign tmp6 = (~B[0])& (~B[1])& A[0];
assign tmp7 = (~B[1])& A[1];
assign tmp8 = (~B[0])& A[1]& A[0];
assign A_greater_B = tmp6 | tmp7 | tmp8;
endmodule
`timescale 10 ps/ 10 ps
// FPGA projects using Verilog/ VHDL
// fpga4student.com
// Verilog testbench code for 2-bit comparator
module tb_comparator;
reg [1:0] A, B;
wire A_less_B, A_equal_B, A_greater_B;
integer i;
// device under test
comparator dut(A,B,A_less_B, A_equal_B, A_greater_B);
initial begin
for (i=0;i<4;i=i+1)
begin
A = i;
B = i + 1;
#20;
end
for (i=0;i<4;i=i+1)
begin
A = i;
B = i;
#20;
end
for (i=0;i<4;i=i+1)
begin
A = i+1;
B = i;
#20;
end
end
endmodule
```

**Finally, simulate the Verilog code and testbench in ModelSim and verify the operation of the comparator through simulation waveform.**

**By observing the waveform, Verilog code for the comparator are working correctly.**

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