fpga4student.com FPGA digital design projects using Verilog/ VHDL: VHDL code for D Flip Flop

Friday, February 3, 2017

VHDL code for D Flip Flop

  VHDL code for D Flip Flop is presented in this project. Verilog code for D Flip Flop here. There are several types of D Flip Flops such as high-level asynchronous reset D Flip-Flop, low-level asynchronous reset D Flip-Flop, synchronous reset D-Flip-Flop, rising edge D Flip-Flop, falling edge D Flip-Flop, which is implemented in VHDL in this project.

VHDL code for D Flip Flop


VHDL code for Rising Edge D Flip Flop:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for rising edge D flip flop 
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;   
      D :in  std_logic    
   );
end RisingEdge_DFlipFlop;
architecture Behavioral of RisingEdge_DFlipFlop is  
begin  
 process(Clk)
 begin 
    if(rising_edge(Clk)) then
   Q <= D; 
    end if;       
 end process;  
end Behavioral; 

VHDL code for Rising Edge D Flip-Flop with Synchronous Reset:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Rising edge D flip flop with Synchronous Reset input 
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_SyncReset is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end RisingEdge_DFlipFlop_SyncReset;
architecture Behavioral of RisingEdge_DFlipFlop_SyncReset is  
begin  
 process(Clk)
 begin 
    if(rising_edge(Clk)) then
   if(sync_reset='1') then 
    Q <= '0';
   else 
    Q <= D; 
   end if;
    end if;       
 end process;  
end Behavioral; 

VHDL code for Rising Edge D Flip-Flop with Asynchronous Reset High Level:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Rising edge D flip flop with Asynchronous Reset high
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_AsyncResetHigh is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end RisingEdge_DFlipFlop_AsyncResetHigh;
architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetHigh is  
begin  
 process(Clk,sync_reset)
 begin 
     if(sync_reset='1') then 
   Q <= '0';
     elsif(rising_edge(Clk)) then
   Q <= D; 
  end if;      
 end process;  
end Behavioral; 

VHDL code for Rising Edge D Flip-Flop with Asynchronous Reset Low Level:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Rising edge D flip flop with Asynchronous Reset low 
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity RisingEdge_DFlipFlop_AsyncResetLow is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end RisingEdge_DFlipFlop_AsyncResetLow;
architecture Behavioral of RisingEdge_DFlipFlop_AsyncResetLow is  
begin  
 process(Clk,sync_reset)
 begin 
     if(sync_reset='0') then 
   Q <= '0';
     elsif(rising_edge(Clk)) then
   Q <= D; 
  end if;      
 end process;  
end Behavioral; 

VHDL code for Falling Edge D Flip Flop:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for falling edge D flip flop 
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;   
      D :in  std_logic    
   );
end FallingEdge_DFlipFlop;
architecture Behavioral of FallingEdge_DFlipFlop is  
begin  
 process(Clk)
 begin 
    if(falling_edge(Clk)) then
   Q <= D; 
    end if;       
 end process;  
end Behavioral; 

VHDL code for Falling Edge D Flip-Flop with Synchronous Reset:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Falling edge D flip flop with Synchronous Reset input 
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop_SyncReset is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end FallingEdge_DFlipFlop_SyncReset;
architecture Behavioral of FallingEdge_DFlipFlop_SyncReset is  
begin  
 process(Clk)
 begin 
    if(falling_edge(Clk)) then
   if(sync_reset='1') then 
    Q <= '0';
   else 
    Q <= D; 
   end if;
    end if;       
 end process;  

end Behavioral;

VHDL code for Falling Edge D Flip-Flop with Asynchronous Reset High Level:


-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Falling edge D flip flop with Asynchronous Reset high 
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop_AsyncResetHigh is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end FallingEdge_DFlipFlop_AsyncResetHigh;
architecture Behavioral of FallingEdge_DFlipFlop_AsyncResetHigh is  
begin  
 process(Clk,sync_reset)
 begin 
     if(sync_reset='1') then 
   Q <= '0';
     elsif(falling_edge(Clk)) then
   Q <= D; 
  end if;      
 end process;  
end Behavioral; 

VHDL code for Falling Edge D Flip-Flop with Asynchronous Reset Low Level:

-- FPGA projects using VHDL/ VHDL 
-- fpga4student.com
-- VHDL code for D Flip FLop
-- VHDL code for Falling edge D flip flop with Asynchronous Reset low  
Library IEEE;
USE IEEE.Std_logic_1164.all;

entity FallingEdge_DFlipFlop_AsyncResetLow is 
   port(
      Q : out std_logic;    
      Clk :in std_logic;  
   sync_reset: in std_logic;  
      D :in  std_logic    
   );
end FallingEdge_DFlipFlop_AsyncResetLow;
architecture Behavioral of FallingEdge_DFlipFlop_AsyncResetLow is  
begin  
 process(Clk,sync_reset)
 begin 
     if(sync_reset='0') then 
   Q <= '0';
     elsif(falling_edge(Clk)) then
   Q <= D; 
  end if;      
 end process;  
end Behavioral; 
Simulation waveform:
VHDL code for D Flip Flop

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