tag:blogger.com,1999:blog-2731449680288404691.post1039663953977088126..comments2024-03-26T19:05:02.262-07:00Comments on FPGA Projects, Verilog Projects, VHDL Projects - FPGA4student.com: Pipelined MIPS Processor in Verilog (Part-1)FPGA4studenthttp://www.blogger.com/profile/11381124680279432980noreply@blogger.comBlogger6125tag:blogger.com,1999:blog-2731449680288404691.post-8727549164410140292020-01-29T08:56:16.944-08:002020-01-29T08:56:16.944-08:00Hi sir,I want code for 64 bit 5 stage pipelinig ri...Hi sir,I want code for 64 bit 5 stage pipelinig risc processor with 32 instructions in double cycle.MY requirements are<br />1.ALU 2.Control unit 3.Shift registers 4.Accumulator registers 5.Memory 6.I/o ports 7.Serial ports<br /> intetisravani11@gmail.comhttps://www.blogger.com/profile/08298285088800189065noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-15917763794968768522018-11-15T22:28:10.567-08:002018-11-15T22:28:10.567-08:00k sir. thank you...how to write constraint file fo...k sir. thank you...how to write constraint file for risc processor in cadencethabsehttps://www.blogger.com/profile/09081916561804691417noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-68946519104232653852018-11-15T22:21:06.934-08:002018-11-15T22:21:06.934-08:00Double check your tool. It should be able to suppo...Double check your tool. It should be able to support Text file reading Verilog code.FPGA4studenthttps://www.blogger.com/profile/11381124680279432980noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-72070072547232399872018-11-14T21:44:55.455-08:002018-11-14T21:44:55.455-08:00Hi sir,
Can you pls tell me, how to give the ...Hi sir,<br /> Can you pls tell me, how to give the instruction data memory in cadence. cadence tool cant accept the text file as input.thabsehttps://www.blogger.com/profile/09081916561804691417noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-83556708171139470762017-12-25T23:25:53.298-08:002017-12-25T23:25:53.298-08:00Instructions that you want to load into the instru...Instructions that you want to load into the instruction memory need to save in the "instr.txt" in the binary format. If you want to save it hexadecimal format, replace the $readmemb instruction by $readmemh instruction in the Verilog code of the instruction memory. FPGA4studenthttps://www.blogger.com/profile/11381124680279432980noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-15426425049104487232017-12-25T21:40:58.494-08:002017-12-25T21:40:58.494-08:00Hi sir,
I executed following program, I am gettin...Hi sir, <br />I executed following program, I am getting 10054 error "can't open design file instr.txt"<br />Anonymoushttps://www.blogger.com/profile/02395746946244814598noreply@blogger.com