tag:blogger.com,1999:blog-2731449680288404691.post4451861976136327436..comments2024-03-26T19:05:02.262-07:00Comments on FPGA Projects, Verilog Projects, VHDL Projects - FPGA4student.com: Verilog Code for 16-bit RISC Processor FPGA4studenthttp://www.blogger.com/profile/11381124680279432980noreply@blogger.comBlogger27125tag:blogger.com,1999:blog-2731449680288404691.post-71562491446731642282020-12-16T05:45:31.793-08:002020-12-16T05:45:31.793-08:00Each instruction/memory data width has 16 bits or ...Each instruction/memory data width has 16 bits or 2 bytes. PC counted by 2. That's why only PC[4:1] is used to fetch instruction from ROM.All About Physical Designhttps://www.blogger.com/profile/03698892711908127742noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-61580878221076471842020-08-04T11:52:14.415-07:002020-08-04T11:52:14.415-07:00Can you please explain why in Instruction memory p...Can you please explain why in Instruction memory part in line <br />wire [3 : 0] rom_addr = pc[4 : 1];<br />you have not assigned pc[3:0]? why u hv left out 0th bit pc while assigning?<br />Akashhttps://www.blogger.com/profile/16070641809178822217noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-45265050665669813772020-06-25T21:13:55.083-07:002020-06-25T21:13:55.083-07:00it can be used for any Verilog simulator. You need...it can be used for any Verilog simulator. You need to create the .data + .prog files in 'test' folder inside the project folder.FPGA4studenthttps://www.blogger.com/profile/11381124680279432980noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-47907994044790707712020-06-07T11:43:43.576-07:002020-06-07T11:43:43.576-07:00Sir, Can you tell me which simulator you used? I t...Sir, Can you tell me which simulator you used? I tried xilinx vivado... but I didnt understand where to check the output for that .data and .prog files.Anonymoushttps://www.blogger.com/profile/17884031703075313594noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-90368072670735144962020-04-18T13:03:26.502-07:002020-04-18T13:03:26.502-07:00Could you explain the abbreviation of rs1,rs2 and ...Could you explain the abbreviation of rs1,rs2 and ws<br />Anirudh Kashyaphttps://www.blogger.com/profile/09000247916499642910noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-17797086528773242412020-04-14T21:53:28.591-07:002020-04-14T21:53:28.591-07:00Can you please send the codes beacuse i have teste...Can you please send the codes beacuse i have tested and it was showing some errors the tool i have used is xilinx 14.3 version and still not showing the outputvvs creationshttps://www.blogger.com/profile/01138477529433228448noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-86741151511189877592020-02-07T00:45:04.187-08:002020-02-07T00:45:04.187-08:00Implementation in vivado says the design is empty....Implementation in vivado says the design is empty. How to solve it ?Akash Bahetrahttps://www.blogger.com/profile/04884053359469577465noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-21265576151578087742020-01-25T02:47:01.468-08:002020-01-25T02:47:01.468-08:00I am new in verilog, using Quartus II for simulati...I am new in verilog, using Quartus II for simulation. Facing syntax error in test.prog but i don't get it where is the error. I have copied your given example as it is and saved it naming test.progmisbah 222https://www.blogger.com/profile/00917062217040138243noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-39657253466821382882020-01-19T21:39:20.017-08:002020-01-19T21:39:20.017-08:00How to create test.data and test.prog files and wh...How to create test.data and test.prog files and where should we create it?<br />Should they be a text file?Anonymoushttps://www.blogger.com/profile/02952537203207673077noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-89002305655347672602020-01-14T06:18:50.249-08:002020-01-14T06:18:50.249-08:00Can u send me the code for 5stage pipeline 64 bit ...Can u send me the code for 5stage pipeline 64 bit Risc processor with 32 instructionsintetisravani11@gmail.comhttps://www.blogger.com/profile/08298285088800189065noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-77870757574193570042020-01-12T23:15:04.905-08:002020-01-12T23:15:04.905-08:00Thanks for the postThanks for the postDruva Kumar CHhttps://www.blogger.com/profile/11668629680593552295noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-52636774598870577572020-01-03T18:21:47.290-08:002020-01-03T18:21:47.290-08:00Can you please provide FSM for each blocks.Can you please provide FSM for each blocks.Mani023https://www.blogger.com/profile/04065744366549620581noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-59649359409846720172018-10-22T22:16:40.103-07:002018-10-22T22:16:40.103-07:00Check register and memory content for verification...Check register and memory content for verification or you take some of them as outputs to see on the simulation waveformFPGA4studenthttps://www.blogger.com/profile/11381124680279432980noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-14997284888973034742018-10-22T02:18:24.324-07:002018-10-22T02:18:24.324-07:00i did not get the output could you please tell me ...i did not get the output could you please tell me how to exactly execute itAnonymoushttps://www.blogger.com/profile/09075448781434272706noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-59840865440025948082018-10-21T17:14:22.842-07:002018-10-21T17:14:22.842-07:00For the instruction memory, you need to convert in...For the instruction memory, you need to convert instructions to machine code. Then, put the data into instruction memory. There are 2 given example files for data and instruction memory. You can refer to it.FPGA4studenthttps://www.blogger.com/profile/11381124680279432980noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-76480288796516226192018-10-21T09:06:00.133-07:002018-10-21T09:06:00.133-07:00 how to create a test.data (Initial content of dat... how to create a test.data (Initial content of data memory) and test.prog (Intruction memory).Anonymoushttps://www.blogger.com/profile/17749455324394478403noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-46528899899177357632018-10-07T06:01:17.321-07:002018-10-07T06:01:17.321-07:00Glad to hear that. You're welcome.Glad to hear that. You're welcome.FPGA4studenthttps://www.blogger.com/profile/11381124680279432980noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-38235836298508329572018-10-05T23:48:30.564-07:002018-10-05T23:48:30.564-07:00Thank you for the above code. I tested it , works ...Thank you for the above code. I tested it , works perfectly. I got an overview now. Thanks again.Marthi SivaRama YajnaNarayana Sarmahttps://www.blogger.com/profile/09015934127401432846noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-13303940158735939952018-09-22T05:04:00.948-07:002018-09-22T05:04:00.948-07:00Can u send 8bit RISC processor code??Can u send 8bit RISC processor code??Neeraj kumarhttps://www.blogger.com/profile/07960674983030062178noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-11433643741284446602018-01-01T09:00:53.413-08:002018-01-01T09:00:53.413-08:00can u pls send me this code
my mail is
manju.upad...can u pls send me this code <br />my mail is<br />manju.upadhya17@gmail.comAnonymoushttps://www.blogger.com/profile/04981858207048350239noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-33699389592289154132017-11-09T17:59:01.821-08:002017-11-09T17:59:01.821-08:00These files were given above. Just create the file...These files were given above. Just create the file with the same names and copy the contents into these files.Anonymoushttps://www.blogger.com/profile/14472547411595467898noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-17884573123452403732017-11-03T22:55:58.497-07:002017-11-03T22:55:58.497-07:00can yo just explain about the test.prog and test.d...can yo just explain about the test.prog and test.data ,where should we create it and also about the .o file.<br />Thanks in advance.rajuhttps://www.blogger.com/profile/18326829739566408323noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-71497758726249974852017-10-29T22:40:30.887-07:002017-10-29T22:40:30.887-07:00to implent it on fpga module like spartan,can you ...to implent it on fpga module like spartan,can you please give a heads up<br />Anonymoushttps://www.blogger.com/profile/14176310453270588241noreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-69831885448815047272017-07-22T08:40:16.495-07:002017-07-22T08:40:16.495-07:00Check the given table to understand the functional...Check the given table to understand the functionality of ALU and ALU control unit.Van Loi Lehttp://fpga4student.comnoreply@blogger.comtag:blogger.com,1999:blog-2731449680288404691.post-75063164097433688592017-07-22T05:02:51.217-07:002017-07-22T05:02:51.217-07:00Description of ALU and ALU Control is still missin...Description of ALU and ALU Control is still missing in the Datapath.Nikhilnoreply@blogger.com