fpga4student.com FPGA digital design projects using Verilog/ VHDL: About

About


Hi,
I'm Van Loi Le from Singapore and I'm a FPGA/ Verilog/ VHDL professional freelancer. I have been working in the FPGA field for six years and I have decided to run this website to give beginners free FPGA Verilog/ VHDL projects and detailed tutorials which are my experiences throughout the years being in the field of FPGA digital design using Verilog/ VHDL. I have done hundreds of projects on FPGA implementation using Verilog/ VHDL and digital logic design using LogiSim, CEDAR Logic. I also have a great experience on electrical and electronic engineering projects such as electronic circuits, MIPS architecture of single-cycle, multi-cycle and pipeline, MIPS/PIC assembly, PCB design and layout, etc. 
I also offer services for FPGA (Xilinx or Altera) projects using Verilog/ VHDL, electrical and electronics engineering, MIPS Assembly using QtSpim or MARS, and Digital Logic Design using Logisim or CEDAR LOGIC. You can see my profile on Freelancer, Quora, or my customer testimonials here
Please do not hesitate to contact me via my email if you are interested in any FPGA/ Verilog/ VHDL projects or you want to discuss about FPGA/ Verilog/ VHDL stuffs. You also can comment on my posts if you have any question.
Thanks.
Best regards,

fpga4student.comVan Loi Le 
FPGA Verilog/ VHDL freelancer
admin@fpga4student.com 
fpga4student.comHire me on Freelancer.com


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