I'm Van Loi Le from Singapore and I'm a FPGA/ Verilog/ VHDL professional freelancer. I have been working in the FPGA field for six years and I have decided to run this blog to give students free FPGA Verilog/ VHDL projects and detailed tutorials which are my experiences throughout the years being in the field of digital design using Verilog/ VHDL. I have done hundreds of projects on FPGA implementation using Verilog/ VHDL and digital logic design using LogiSim, CEDAR Logic. I also have a great experience on electrical and electronic engineering projects such as electronic circuits, MIPS architecture of single-cycle, multi-cycle and pipeline, MIPS/PIC assembly, PCB design and layout, etc.
Please do not hesitate to contact me via my email if you are interested in any projects or you want to have any discussions related to the posts on my blog. You also can comment on my posts to discuss.
Van Loi Le