Car Parking System in VHDL

This VHDL project presents a car parking system in VHDL using Finite State Machine (FSM). VHDL code and testbench for the car parking system are fully provided.

The VHDL car parking system is shown in the following figure. There is a front sensor to detect vehicles going to the gate of the car parking system. Another back sensor is to detect if the coming vehicle passed the gate and getting into the car park. 

VHDL code for single-port RAM

This VHDL post presents a VHDL code for a single-port RAM (Random Access Memory). The VHDL testbench code is also provided to test the single-port RAM in Xilinx ISIM. The RAM's size is 128x8 bit.

VHDL code for Comparator

This VHDL project presents a simple VHDL code for a comparator which is designed and implemented in Verilog before. Full VHDL code together with test bench for the comparator is provided.

The design for the comparator based on the truth table and K-map are already presented here. There are two 2-bit inputs A and B to be compared. Three output signals are A_less_B (1 if A < B, else 0), A_equal_B (1 if A=B, else 0), and A_greater_B (1 if A>B, else 0). The minimized expressions obtained from K-Map tables for the outputs are used for VHDL coding of the comparator.

Verilog code for PWM generator

This Verilog project presents a Verilog code for PWM generator with Variable Duty Cycle. Last time, I presented a VHDL code for a PWM generator.

The Verilog PWM (Pulse Width Modulation) generator creates a 10MHz PWM signal with variable duty cycle. Two buttons which are debounced are used to control the duty cycle of the PWM signal. The first push button is to increase the duty cycle by 10%, and the other button is to decrease the duty cycle by 10%. 

VHDL code for Traffic light controller

A VHDL code for a traffic light controller on FPGA is presented. The traffic light controller in VHDL is used for an intersection between highway and farm way. 

There is a sensor in the farm way side to detect if there is any vehicle on the farm way. If vehicles are detected on the farm way, traffic light on the high way turns to YELLOW, then RED so that the vehicles from the farm way can cross the high way. Otherwise, the traffic light on the high way is always GREEN and traffic light on the farm way is always RED. The time period is 3 seconds for the YELLOW light and 10 seconds for the RED light. 

VHDL code for debouncing buttons on FPGA

When pressing buttons on FPGA, there are unpredictable bounces that are unwanted. This VHDL code is to debounce buttons on FPGA by only generating a single pulse with a period of the input clock when the button on FPGA is pressed, held long enough, and released. Last time, I presented a simple Verilog code for debouncing buttons on FPGA.

This VHDL project is to present a VHDL code for debouncing buttons on FPGA. Full VHDL code and testbench are provided.

How to generate a clock enable signal on FPGA

This post is about to tell you how to generate a clock enable signal (not gated clocks) to drive another logic using the same clock domain instead of creating another clock (using clock dividers or clock gating) possibly causing FPGA timing issues (as created by non-dedicated FPGA clock generators) or clock domain crossing problems such as metastability, data loss, and data incoherency if it is not taken care. 

Verilog code for Clock divider on FPGA

Last time, I presented a VHDL code for a clock divider on FPGA. This Verilog project provides full Verilog code for the Clock Divider on FPGA together with Testbench for simulation. The Verilog clock divider is simulated and verified on FPGA.

VHDL Code for Clock Divider on FPGA

This VHDL project presents a full VHDL code for clock divider on FPGA. Testbench VHDL code for clock divider is also provided. The VHDL code for the clock divider is synthesizable and verified on FPGA.

Verilog vs VHDL: Explain by Examples

Last time, I presented in detail what actually FPGA programming is and how to get started with FPGA design. A brief history of Verilog and VHDL was also discussed. If you search for the difference between Verilog and VHDL, you will see many difference pages discussing this HDL language war, but most of them are short and not well-explained by examples for facilitating beginners or students' understanding.

The difference between Verilog and VHDL will be explained in detail by examples in this post. The advantages and disadvantages of Verilog and VHDL will be also discussed.

What is FPGA Programming?

Last time, I presented in detail what exactly an FPGA is and the advantage of FPGAs over ASICs and microcontrollers. FPGAs are nothing, but reconfigurable logic blocks and interconnects can be programmed by Hardware Description Language like Verilog/ VHDL to perform a specific functionality.

Today, I will present what actually FPGA programming is, how to get started with FPGA programming, and FPGA programming design flow. The difference between FPGA programming and software programming will be also discussed.

Altera FPGA boards for beginners

Last time, I presented my four recommended and affordable Xilinx FPGA boards for beginners. The recommended Xilinx FPGA boards offer good enough number of IO devices and supporting circuits for student projects or practice, and more importantly, the FPGA boards are affordable for beginners or students.

In this FPGA post, I will present another four recommended and affordable Altera FPGA boards for beginners. These Altera FPGA boards are also very cheap and well-designed for students or beginners. 

1. Cyclone IV Altera FPGA Board from Aliexpress (33.69USD)