Verilog Code for Multiplier using Carry-Look-Ahead Adders

This project is to implement a parameterized multiplier using carry-look-ahead adders in Verilog. The Verilog code for the multiplier is provided.

Users can change the number of bits of the multiplier by modifying the predefined parameters. The parameters such as MULTICAND_WID and MULTIPLIER_WID are to define the number of bits of the multiplicand and multiplier, and when we want to change the number of bits, just change these parameters and re-synthesize or simulate.

Verilog code for Microcontroller (Part 3- Verilog code)

In this project, Verilog code for a microcontroller is presented. The microcontroller architecture and instruction set are shown in part 1 and part 2. 

Verilog code for microcontroller (Part-2- Design)

In this post, architecture design for the microcontroller is presented. Verilog code for the microcontroller is posted in part 3.

The following diagram is the architecture of the microcontroller. The datapath is shown as black arrows, and control signals are red arrows.

Verilog code for Microcontroller (Part 1 - Specification)

In this project, Verilog code for a microcontroller is presented. Before implementing, the instruction set architecture for the microcontroller is presented in this part. (Part-2 and Part-3)

Floating point numbers in MIPS Assembly

Floating point numbers in MIPS assembly is presented in this project. 

A lot of FPGA/ Verilog/ VHDL are posted and today I want to post a MIPS assembly project. MIPS is a very common microprocessor being taught in many universities and there are a lot of FPGA/ Verilog/ VHDL projects on implementing MIPS processor based on a provided Instruction set. After the MIPS is implemented, we can program the MIPS by downloading the MIPS assembly code into the instruction memory. 

This is a very simple MIPS Assembly code for students to play with floating point numbers. The simulator being used is Qtspim and for the instruction set of MIPS architecture, you can visit here. Users will enter eight floating point numbers and the program finds the minimum, maximum and average number of the entered floating point numbers.

The output console is as follows:

N-bit ring counter in VHDL

This VHDL project is to implement a parameterized N-bit switch tail ring counter using VHDL. VHDL code for parameterized ring counter is presented in this project.

It means that users can easily change the number of bits of the ring counter without modifying VHDL code inside the ring counter. There is a parameter N to define the number of bits of the ring counter, and when we want to change the number of bits, just change the parameter N and re-synthesize or simulate. 

VHDL code for digital clock on FPGA

This VHDL project is the VHDL version code of the digital clock in Verilog I posted before(link). The VHDL code for the digital clock is synthesizable for FPGA implementation and full VHDL code is provided.

This digital clock is a reconfigurable 24-hour clock displaying hours, minutes, and seconds on seven-segment LEDs (Tutorials on 7-segment LEDs: here). Besides, users can manually set the time of the digital clock including hours and minutes through switches. 

Verilog code for 4x4 Multiplier

This project is to implement a 4x4 multiplier using Verilog HDL. Full Verilog code for the multiplier is presented. 

The technique being used is shift/add algorithm, but the different feature is using a two-phase self-clocking system in order to reduce the multiplying time by half.

Verilog code for Car Parking System

This simple project is to implement a car parking system in Verilog. The Verilog code for the car parking system is fully presented.

In the entrance of the parking system, there is a sensor which is activated to detect a vehicle coming. Once the sensor is triggered, a password is requested to open the gate. If the entered password is correct, the gate would open to let the vehicle get in. Otherwise, the gate is still locked. If the current car is getting in the car park being detected by the exit sensor and another the car comes, the door will be locked and requires the coming car to enter passwords.

Image processing on FPGA using Verilog HDL

This FPGA project is aimed to show in details how to process an image using Verilog from reading an input bitmap image (.bmp) in Verilog, processing and writing the processed result to an output bitmap image in Verilog. The full Verilog code for reading image, image processing, and writing image is provided.

VHDL code for 8-bit Comparator

VHDL code for a 8-bit comparator is presented in this post. 74F521 is an 8-bit identity comparator which provides the low output if two 8-bit inputs are matched. 

Below are the truth table and symbol of the comparator.

Truth table

How to load a text file or an image into FPGA

This FPGA tutorial presents two ways to load a text file or an image into FPGA using Verilog or VHDL for image processing. It can be really useful for functional verifications in real-time FPGA image processing projects.

16-bit CPU design in LogiSim

A 16-bit CPU design in Logisim is presented. The 16-bit simple CPU with data-path and control unit is shown as below:

Figure 1. Block diagram of a 16-bit simple CPU

Verilog code for Traffic light controller

A Verilog source code for a traffic light controller on FPGA is presented. A sensor on the farm is to detect if there are any vehicles and change the traffic light to allow the vehicles to cross the highway. Otherwise, highway light is always green since it has higher priority than the farm. 

Verilog code for Alarm clock on FPGA

Verilog code for an alarm clock on FPGA is presented in this project. The Verilog code is fully synthesizable for FPGA implementation. 

The simple alarm clock is shown in the following figure. The alarm clock outputs a real-time clock with a 24-hour format and also provides an alarm feature. Users also can set the clock time through switches. 

Dynamically allocating memory in MIPS Assembly

MIPS Assembly Dynamically Allocating memory example:

Enter player's name, points and minutes, and then sorting using dynamically allocating techniques. 

Expected results: