How to load a text file or an image into FPGA

This FPGA tutorial presents two ways to load a text file or an image into FPGA using Verilog or VHDL for image processing. It can be really useful for functional verifications in real-time FPGA image processing projects.


The first way is to load a text file or an image into memory by reading the binary/hexadecimal file using Verilog/ VHDL code.

It is noted that Verilog/VHDL cannot read image file directly, but they can read binary text files. Therefore, the image is required to be converted into binary text files and then use Verilog/VHDL to read it. An image can be easily converted to hexadecimal/ binary data using Matlab, C, Python, etc.

For Verilog code, you can use $readmemh(for hexadecimal data) or $readmemb(for binary data) command to load a converted binary/hexadecimal text file directly. Example Verilog code for loading a text file or an image into FPGA using $readmemh: here

For VHDL code, the TEXTIO package provides necessary commands to read binary text files. Details of the VHDL tutorial on reading image/text file in VHDL can be found here. Another example VHDL code for loading a text file or an image into FPGA: here

The second way to load a text file or an image file into FPGA is to initialize it as the initial values of the block memory:

1. If you are using Altera FPGA, you can use Mega-Function in the MegaWizard Plug-In Manager in Quartus II to initialize a block memory with the text file or image-converted binary text file in the MIF format. A sample .mif file is here.

You can read more details the process how to use Megafunction in Altera as follows: User guide memory initialization

2. If you are using Xilinx FPGA, use the Core Generator in Xilinx ISE or IP core in Vivado to generate a block memory with the initial content as the text file or image-converted binary text files. The initial data file must be in .coe format. A sample .coe file is here.

You can read more details how to generate a block memory using CORE Generator in Xilinx ISE: Block memory Generator Xilinx
Recommended FPGA projects for students:

10 comments:

  1. how to implement usb 2.0 protocol on fpga(spartan 3e evaluation board)

    ReplyDelete
    Replies
    1. You need to study how USB works and understand the specification of USB 2.0. Then you can design circuits to implement the protocol.

      Delete
  2. where can i study how to implement and FPGA ALTERA.. i just wanna the base for start the implementation

    ReplyDelete
  3. You can check some tutorial videos on Youtube and practice simple FPGA projects on fpga4student.com

    ReplyDelete
  4. how to convert the RGB image into gray scale image and then to binary image in verilog HDL

    ReplyDelete
    Replies
    1. For simplicity, just use this formula for converting RGB to Gray scale image:
      Gray = (R + G + B) / 3.
      Read binary image in Verilog, follow the following tutorial:
      http://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html

      Delete
  5. Sir,
    I successfully stored a image into BRAM of NEXYS 4 DDR and displayed the same on VGA monitor. But I am facing problem of storing complete image, because my BRAM size is not sufficient, can you please guide me any other possible solution to store 1280x1024 image

    ReplyDelete
    Replies
    1. If the image size is bigger than BRAM of your FPGA, you can not store the image completely. You can do a trick like this: Every 4 or 8 or 16 pixels you only store 1 pixel. You can refer to this: https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html
      However, the image quality is not good as storing the complete image.

      Delete
  6. Sir,
    Can u please guide me how to store 1280x1024 pixel image into FPGA. I am using Nexus 4 ddr board.

    ReplyDelete
    Replies
    1. If the image size is bigger than BRAM of your FPGA, you can not store the image completely. You can do a trick like this: Every 4 or 8 or 16 pixels you only store 1 pixel. You can refer to this: https://www.fpga4student.com/2016/11/image-processing-on-fpga-verilog.html
      However, the image quality is not good as storing the complete image.

      Delete

Trending FPGA Projects