Shifter Design in VHDL

In this VHDL project, a shifter with the ability to shift and rotate data, which is mainly used in the permutation and transpositions of ciphers, will be implemented in VHDL. The VHDL shifter is a key component in the upcoming co-processor's processing unit. Fast shifting and rotating functions are critical for cryptographic applications.

VHDL code for the shifter will be presented together with its testbench VHDL code for functional simulation.

VHDL code for Shifter

The input/ output interface of the shifter is shown in the above figure. The shifter instruction set is as follows:

  • SHIFT_Ctrl = "1000": SHIFTOUT <= Rotate SHIFTINPUT >>8
  • SHIFT_Ctrl = "1001": SHIFTOUT <= Rotate SHIFTINPUT >>4
  • SHIFT_Ctrl = "1010": SHIFTOUT <= Shift Left Logical SHIFTINPUT << 8

VHDL code for the shifter:

library IEEE;
-- FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for Shifter
entity shifter is
  generic ( N: integer:=16
    Port ( SHIFTINPUT : in  STD_LOGIC_VECTOR(N-1 downto 0);
   SHIFT_Ctrl : in  STD_LOGIC_VECTOR(3 downto 0); 
   SHIFTOUT: out  STD_LOGIC_VECTOR(N-1 downto 0)
end shifter;

architecture Behavioral of shifter is

case(SHIFT_Ctrl) is
when "1000" => SHIFTOUT <= SHIFTINPUT(7 downto 0)&SHIFTINPUT(15 downto 8);-- ROR8
when "1001" => SHIFTOUT <= SHIFTINPUT(3 downto 0)&SHIFTINPUT(15 downto 4);-- ROR4
when "1010" => SHIFTOUT <= SHIFTINPUT(7 downto 0) & "00000000"; -- SLL8
when others => SHIFTOUT <= x"0000";
end case;
end process;

end Behavioral;

Testbench VHDL code for the shifter:

USE ieee.std_logic_1164.ALL;
-- FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for Shifter
-- VHDL testbench code for Shifter
ENTITY tb_shifter IS
END tb_shifter;
ARCHITECTURE behavior OF tb_shifter IS 
    -- Component Declaration for Shifter
    COMPONENT shifter
         SHIFTINPUT : IN  std_logic_vector(15 downto 0);
         SHIFT_Ctrl : IN  std_logic_vector(3 downto 0);
         SHIFTOUT : OUT  std_logic_vector(15 downto 0)
   signal SHIFTINPUT : std_logic_vector(15 downto 0) := (others => '0');
   signal SHIFT_Ctrl : std_logic_vector(3 downto 0) := (others => '0');
   signal SHIFTOUT : std_logic_vector(15 downto 0);
 -- Instantiate the Shifter
   uut: shifter PORT MAP (
          SHIFT_Ctrl => SHIFT_Ctrl,

   -- Stimulus process for shifter
   stim_proc: process
      SHIFTINPUT <= x"0044";
      wait for 100 ns; 
  SHIFT_Ctrl <= "1000";-- ROR8
  wait for 100 ns; 
  SHIFT_Ctrl <= "1001";-- ROR4
  wait for 100 ns; 
  SHIFT_Ctrl <= "1010";-- SLL8
   end process;


Synthesized RTL Schematic for the shifter:

Shifter Design in VHDL

Simulation Waveform for the shifter:

Shifter Design in VHDL

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