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Saturday, April 29, 2017

Simple Verilog code for debouncing buttons on FPGA

This post is to present a simple debouncing Verilog code for buttons on FPGA. Mechanical switches/ buttons cause the unpredictable bounce in the signal when toggled. There are various ways to implement debouncing circuits for buttons on FPGA. In this project, a simple debouncing circuit is implemented in Verilog to generate only a single pulse when pressing a button on FPGA

Verilog code for button debouncing

Debouncing Circuit for buttons on FPGA

As shown in the figure below, when a button on FPGA is pressed and released, there are many unexpected up-and-down bounces in push button signal. The debouncing circuit only generates a single pulse with a period of the slow clock without bouncing as we expected. 

Verilog code for button debouncing

Expected waveform from the debouncing circuit


Verilog code for button debouncing on FPGA:

//fpga4student.com
// FPGA projects, Verilog projects, VHDL projects
// Verilog code for button deboucing on FPGA
// debouncing module 
module debounce(input pb_1,clk,output pb_out);
wire slow_clk;
wire Q1,Q2,Q2_bar;
clock_div u1(clk,slow_clk);
my_dff d1(slow_clk, pb_1,Q1 );
my_dff d2(slow_clk, Q1,Q2 );
assign Q2_bar = ~Q2;
assign pb_out = Q1 & Q2_bar;
endmodule
// Slow clock for debouncing 
module clock_div(input Clk_100M, output reg slow_clk

    );
    reg [26:0]counter=0;
    always @(posedge Clk_100M)
    begin
        counter <= (counter>=249999)?0:counter+1;
        slow_clk <= (counter < 125000)?1'b0:1'b1;
    end
endmodule
// D-flip-flop for debouncing module 
module my_dff(input DFF_CLOCK, D, output reg Q);

    always @ (posedge DFF_CLOCK) begin
        Q <= D;
    end

endmodule

Simulation waveform for button debouncing:

Verilog code for button debouncing

As shown in the waveform, only a single pulse is generated when a button is pressed and released as expected.
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