fpga4student.com fpga4student.com - Simple Verilog code for debouncing buttons on FPGA

Simple Verilog code for debouncing buttons on FPGA

This post is to present a simple debouncing Verilog code for buttons on FPGA. 

Mechanical switches/ buttons cause the unpredictable bounce in the signal when toggled. There are various ways to implement debouncing circuits for buttons on FPGA. In this project, a simple debouncing circuit is implemented in Verilog to generate only a single pulse when pressing a button on FPGA. 

Verilog code for button debouncing

Debouncing Circuit for buttons on FPGA

As shown in the figure below, when a button on FPGA is pressed and released, there are many unexpected up-and-down bounces in push button signal. The debouncing circuit only generates a single pulse with a period of the slow clock without bouncing as we expected. 

Verilog code for button debouncing

Expected waveform from the debouncing circuit

Verilog code for button debouncing on FPGA:

// FPGA projects, Verilog projects, VHDL projects
// Verilog code for button deboucing on FPGA
// debouncing module 
module debounce(input pb_1,clk,output pb_out);
wire slow_clk;
wire Q1,Q2,Q2_bar;
clock_div u1(clk,slow_clk);
my_dff d1(slow_clk, pb_1,Q1 );
my_dff d2(slow_clk, Q1,Q2 );
assign Q2_bar = ~Q2;
assign pb_out = Q1 & Q2_bar;
// Slow clock for debouncing 
module clock_div(input Clk_100M, output reg slow_clk

    reg [26:0]counter=0;
    always @(posedge Clk_100M)
        counter <= (counter>=249999)?0:counter+1;
        slow_clk <= (counter < 125000)?1'b0:1'b1;
// D-flip-flop for debouncing module 
module my_dff(input DFF_CLOCK, D, output reg Q);

    always @ (posedge DFF_CLOCK) begin
        Q <= D;


Simulation waveform for button debouncing:

Verilog code for button debouncing

As shown in the waveform, only a single pulse is generated when a button is pressed and released as expected.

Recommended Verilog projects:
2. Verilog code for FIFO memory
3. Verilog code for 16-bit single-cycle MIPS processor
4. Programmable Digital Delay Timer in Verilog HDL
5. Verilog code for basic logic components in digital circuits
6. Verilog code for 32-bit Unsigned Divider
7. Verilog code for Fixed-Point Matrix Multiplication
8. Plate License Recognition in Verilog HDL
9. Verilog code for Carry-Look-Ahead Multiplier
10. Verilog code for a Microcontroller
11. Verilog code for 4x4 Multiplier
12. Verilog code for Car Parking System
13. Image processing on FPGA using Verilog HDL
14. How to load a text file into FPGA using Verilog HDL
15. Verilog code for Traffic Light Controller
16. Verilog code for Alarm Clock on FPGA
17. Verilog code for comparator design
18. Verilog code for D Flip Flop
19. Verilog code for Full Adder
20. Verilog code for counter with testbench
21. Verilog code for 16-bit RISC Processor
22. Verilog code for button debouncing on FPGA
23. How to write Verilog Testbench for bidirectional/ inout ports
28. Verilog code for Decoder
29. Verilog code for Multiplexers

No comments:

Post a Comment