How to write Verilog Testbench for bidirectional/ inout ports

This post describes how to write a Verilog testbench for bidirectional or inout ports. This happens in special designs which contain bidirectional or inout ports such as I2C core, IO pads, memories, etc. 

In this post, I will give an example how to write testbench code for a digital IO pad. Basically, the IO pad has logic inputs DS, OEN, IE, PE to configure the IO pad as an input or output. When DS = OEN = IE = PE = 1, the IO pad operates as an input pad. Thus, the data from the bidirectional port PAD are written into the output C. When DS = PE =1 and OEN = IE = 0, the IO pad operates as an output pad. Therefore, the signal from the input I is passed to the bidirectional port PAD.
Verilog testbench for bidirectional/ inout port

Block diagram of the Verilog testbench

As shown in the block diagram of the Verilog testbench, the IO pad under test is the DUT block.  Block 0 controls the inout port PAD as follows:


assign PAD = wr==1 ? din:1'bz;

When wr==1, the inout port PAD operates as an input, so PAD = din. When wr==0, the inout port PAD is assigned to a high impedance 1'bz. Thus, it becomes an output to get data from the input I of the IO pad.
Block 1 is the main testbench to generate test cases to check the input/ output functionality of the IO pad.

Below is the full Verilog testbench for the IO pad.

`timescale 1ns/10ps
// fpga4student.com
// FPGA projects, Verilog projects, VHDL projects
// How to write a verilog testbench for bidirectional/ inout port 
module test_IO();

reg DS,OEN,IE,PE,I,din;
wire PAD;
reg wr;
wire C;
// inout port
assign PAD = wr==1 ? din:1'bz;

DIGITAL_IO dut(I,DS,OEN,PAD,C,PE,IE);

initial begin
 // test the pad as an input
 wr=1;
 DS=1;
 OEN=1;
 din=0;
 IE=1;
 PE=1;
 #100;
 din=1;
 #100;
 din=0; 
 #100;
 din=1;
 #100;
 din=0;
 #100;
 din=1;
 #100;
 din=0;
 #100;
 din=1;
 #100;
 din=0; 
 #100;
 wr=0;
 // test the pad as an output
 // by reading data out 
 #1000;
 DS=1;
 OEN=0;
 din=0;
 IE=0;
 PE=1;
 I=1;
 #100;
 I=0; 
 #100; 
 I=1;
 #100;
 I=0; 
 #100;
 I=1;
 #100;
 I=0; 
 #100;
 end 

endmodule 

Simulation waveform for the bidirectional port:

Verilog testbench for bidirectional/ inout port

The simulation waveform shows that when wr= DS = OEN = IE = PE = 1, the IO pad operates as an input pad and the signal from bidirectional port PAD is passed to the output C. When DS = PE =1 and OEN = IE = 0, wr=0 enables the IO pad operating as an output pad. Therefore, the signal from the bidirectional port PAD is read from the input port I.
In short, the takeaway stuff is the following 'assign' Verilog statement:

assign PAD = (wr==1) ? din:1'bz;

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