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Sunday, November 6, 2016

VHDL code for the 8-bit 74F521 Identity Comparator

Verilog code for a comparator is presented. 74F521 is a 8-bit identity comparator which provides low output if two 8-bit input are matched. 

Below is the symbol of the comparator.
VHDL code for comparator


Truth table

VHDL code for comparator
Logic symbol of the comparator

VHDL code for comparator
Logic diagram (from datasheet of 74L521)

     VHDL code for the 8-bit comparator:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator is
port (
      clock: in std_logic; 
      -- clock for synchronization
      A,B: in std_logic_vector(7 downto 0); 
      -- Two inputs
      IAB: in std_logic; -- Expansion input ( Active low)
      Output: out std_logic -- Output = 0 when A = B 
);
end comparator;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0); -- temporary variables
signal Result: std_logic;
begin

AB(0) <= (not A(0)) xnor (not B(0));         
        -- combinational circuit
AB(1) <= (not A(1)) xnor (not B(1)); 
AB(2) <= (not A(2)) xnor (not B(2)); 
AB(3) <= (not A(3)) xnor (not B(3)); 
AB(4) <= (not A(4)) xnor (not B(4)); 
AB(5) <= (not A(5)) xnor (not B(5)); 
AB(6) <= (not A(6)) xnor (not B(6)); 
AB(7) <= (not A(7)) xnor (not B(7)); 
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
process(clock)
begin
if(rising_edge(clock))then
  if(AB = x"FF" and IAB = '0') then         
         -- check whether A = B and IAB =0 or not
            Result <= '0';
   else
    Result <= '1';
   end if;
end if;
end process;
Output <= Result;
end Behavioral;


Testbench VHDL code:

--------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
ENTITY tb_comparator IS
END tb_comparator;
ARCHITECTURE behavior OF tb_comparator IS 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT comparator
    PORT(
         clock : IN  std_logic;
         A : IN  std_logic_vector(7 downto 0);
         B : IN  std_logic_vector(7 downto 0);
         IAB : IN  std_logic;
         Output : OUT  std_logic
        );
    END COMPONENT
   --Inputs
   signal clock : std_logic := '0';
   signal A : std_logic_vector(7 downto 0) := (others => '0');
   signal B : std_logic_vector(7 downto 0) := (others => '0');
   signal IAB : std_logic := '0';
 --Outputs
   signal Output : std_logic;
   -- Clock period definitions
   constant clock_period : time := 10 ns;
 BEGIN
  -- Instantiate the Unit Under Test (UUT)
   uut: comparator PORT MAP (
          clock => clock,
          A => A,
          B => B,
          IAB => IAB,
          Output => Output
        );
   -- Clock process definitions
   clock_process :process
   begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
   end process;
    -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;
A <= x"AA";
B <= x"BB";
      wait for clock_period*10;
B <= x"AA";
      -- insert stimulus here 
      wait;
   end process;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
END;

Simulation waveform:

verilog/ VHDL code for 8-bit comparator

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