fpga4student.com FPGA digital design projects using Verilog/ VHDL: Two ways to load a text file into FPGA or the initial values to a memory in Verilog/ VHDL (synthesizable)

Sunday, November 6, 2016

Two ways to load a text file into FPGA or the initial values to a memory in Verilog/ VHDL (synthesizable)

The first way is to load the text file or image into memory by initializing it in Verilog/ VHDL code:

 load a text file into FPGA

       1. Verilog example code:

// fpga4student.com FPGA projects 
// Verilog projects, VHDL projects
reg [15:0] rom[15:0];
       initial
       begin
        rom[0] = 16'b1000000110000000;
        rom[1] = 16'b0010110011100100;
        rom[2] = 16'b1100010000000011;
        rom[3] = 16'b0001000111000000;
        rom[4] = 16'b1110110110000001;
        rom[5] = 16'b1100000001111011
        rom[6] = 16'b0100001000000000;
        rom[7] = 16'b0010000000001000;
        rom[8] = 16'b0011000010000000;
        rom[9] = 16'b0000000000000000;
        rom[10] = 16'b0000000000100000;
        rom[11] = 16'b0000000110000000;
        rom[12] = 16'b0001100000000000;
        rom[13] = 16'b0100000010000000;
        rom[14] = 16'b0000100110000000;
        rom[15] = 16'b0100010000010000;
       end

     2. VHDL example code:

-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
subtype your_word is std_logic_vector(7 downto 0);
type your_array is array (0 to 63) of your_word;
constant rom : your_array := ( "00001011",
"00000010","00000001","00000001",
"00000010","00000010","00000001",
"00000001","00000010","00000001",
"00001010","00000010","00000010",
"00000001","00000011","00000001",
"00000001","00000001","00001000",
"00000010","00000001","00000001",
"00000001","00011110","00000000",
"00001001","00000111","00000111",
"00000000","00000000","00000101",
"00001100","00000100","00001000",
"00000000","00000000","00000000", 
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000",
"00000000","00000000","00000000");

    By doing so, the initial values would be loaded into FPGA during synthesis. In case that you want to load a text file into FPGA, you have to convert the text file to binary data and initialize it in Verilog/ VHDL code. A text file can be easily converted to binary data using Matlab code. For verilog code, you can also use $readmemh(for hexadecimal data) or $readmemb(for binary data) command to load a converted text file directly.

The second way to load a text file into FPGA:  


       1. If you are using Altera FPGA, you can use megafunction in the MegaWizard Plug-In Manager in Quartus II to initialize a block memory to store a text file with an initialization data file. You text file should be converted to your_text_file.mif as the memory initialization file which contains the binary data of the text file. A sample mif file is here.

load text file into FPGA using Verilog/ VHDL




  You can read more details the process how to use Megafunction in the Altera website: User guide memory initialization

      2. If you are using Xilinx FPGA, Xilinx has Core Generator to generate a block memory with initialization content. The initial data file is in format .coe. A sample coe file is here or below:

load text file into FPGA using Verilog/ VHDL

Below is an example of COE file.
; An initialization file for a
; 16-bit wide by 8 deep RAM
memory_initialization_radix = 16;
memory_initialization_vector = 0000, 1111, 2222, 3333, 4444, 5555, 6666, 7777;

You can read more details how to generate a block memory using CORE Generator in Xilinx ISE :
Block memory Generator Xilinx
Example loading text file into FPGA and running on FPGA: here
How to load a text file in a testbench Verilog/ VHDL code for simulation:
- For Verilog testbench code: here

- For VHDL testbench code: here

More Verilog/ VHDL projects


You might also like this:
VHDL code for D Flip Flop
Verilog code for D Flip Flop
Verilog code for a comparator
Verilog code for FIFO memory
VHDL code for FIFO memory

15 comments:

  1. Replies
    1. Thanks. Please keep update the blog: https://fpga4student.blogspot.com

      Delete
  2. No problem. If you want to get FPGA Verilog VHDL projects for free, please come to this site to get detailed tutorials. Thanks

    ReplyDelete
  3. I can't simulate? I failed "Index range 4 downto 0 is not compatible with index subtype (1 to 2147483647) of std.standard.string." at "generic (
    stim_file: string := "sim2.dat" ); "
    please help me?

    ReplyDelete
    Replies
    1. Please send me your full code and sim2.dat. I will help to debug.

      Delete
    2. library ieee;
      use ieee.std_logic_1164.all;

      use std.textio.all;
      use work.txt_util.all;

      entity FILE_READ is
      generic (
      stim_file: string := "sim.txt"
      );
      port(
      CLK : in std_logic;
      RST : in std_logic;
      Y : out std_logic_vector(4 downto 0);
      EOG : out std_logic
      );
      end FILE_READ;

      architecture read_from_file of FILE_READ is
      file stimulus: TEXT open read_mode is stim_file;
      begin
      receive_data: process
      variable l: line;
      variable s: string(y'range);
      begin
      EOG <= '0';
      wait until RST='1';
      wait until RST='0';
      while not endfile(stimulus) loop
      readline(stimulus, l);
      read(l, s);
      Y <= to_std_logic_vector(s);
      wait until CLK = '1';
      end loop;
      print("I@FILE_READ: reached end of "& stim_file);
      EOG <= '1';
      wait;
      end process receive_data;
      end read_from_file;

      Delete
    3. mình lưu file sim.txt ở ổ đĩa c nó chứa các giá trị nhị phân 1 và 0 thôi.
      và mục đích của mình là mình muốn cứ mỗi xung clock thì mình đọc về 1 giá trị nhị phân từ 1 file .bin
      bạn có thể sửa lại code giúp mình với ?

      Delete
    4. Hi Luc,
      Bữa giờ bận giờ mới reply bạn đc, bạn gửi file sim.txt và code qua email : admin@fpga4student.com rồi mình sẽ sửa code cho bạn nhé.

      Delete
    5. mình có mail cho bạn rồi ha :)

      Delete
    6. Check mail di ban. Minh gui cho ban 1 code testbench don gian read binary text file cua ban roi nhe.

      Delete
  4. how to implement usb 2.0 protocol on fpga(spartan 3e evaluation board)

    ReplyDelete
    Replies
    1. You need to study how USB works and understand the specification of USB 2.0. Then you can design circuits to implement the protocol.

      Delete