How to load a text file or an image into FPGA

This project presents two ways to load a text file or an image into FPGA using Verilog or VHDL for data/ image processing.

The first way is to load a text file or an image into memory by initializing it in Verilog/ VHDL code:

 load a text file into FPGA

       1. Verilog example code:

// FPGA projects 
// Verilog projects, VHDL projects
reg [15:0] rom[15:0];
        rom[0] = 16'b1000000110000000;
        rom[1] = 16'b0010110011100100;
        rom[2] = 16'b1100010000000011;
        rom[3] = 16'b0001000111000000;
        rom[4] = 16'b1110110110000001;
        rom[5] = 16'b1100000001111011
        rom[6] = 16'b0100001000000000;
        rom[7] = 16'b0010000000001000;
        rom[8] = 16'b0011000010000000;
        rom[9] = 16'b0000000000000000;
        rom[10] = 16'b0000000000100000;
        rom[11] = 16'b0000000110000000;
        rom[12] = 16'b0001100000000000;
        rom[13] = 16'b0100000010000000;
        rom[14] = 16'b0000100110000000;
        rom[15] = 16'b0100010000010000;

     2. VHDL example code:

-- FPGA projects, Verilog projects, VHDL projects
subtype your_word is std_logic_vector(7 downto 0);
type your_array is array (0 to 63) of your_word;
constant rom : your_array := ( "00001011",

By doing so, the initial values would be loaded into FPGA during synthesis. In case that you want to load a text file into FPGA, you have to convert the text file to binary data and initialize it in Verilog/ VHDL code. A text file or an image can be easily converted to binary data using Matlab code. Example Matlab code: here.
For Verilog code, you can also use $readmemh(for hexadecimal data) or $readmemb(for binary data) command to load a converted text file directly. Example Verilog code for loading a text file or an image into FPGA using $readmemh: here
Another example VHDL code for loading a text file or an image into FPGA: here.

The second way to load a text file or an image file into FPGA:  

   1. If you are using Altera FPGA, you can use mega-function in the MegaWizard Plug-In Manager in Quartus II to initialize a block memory to store a text file with an initialization data file. Your text file should be converted to your_text_file.mif as the memory initialization file which contains the binary data of the text file. A sample .mif file is here.

load text file into FPGA using Verilog/ VHDL

    You can read more details the process how to use Megafunction in the Altera website: User guide memory initialization

   2. If you are using Xilinx FPGA, Xilinx has Core Generator to generate a block memory with initialization content. The initial data file is in format .coe. A sample .coe file is here or below:

load text file into FPGA using Verilog/ VHDL

Below is an example of COE file.
; An initialization file for a
; 16-bit wide by 8 deep RAM
memory_initialization_radix = 16;
memory_initialization_vector = 0000, 1111, 2222, 3333, 4444, 5555, 6666, 7777;

You can read more details how to generate a block memory using CORE Generator in Xilinx ISE: Block memory Generator Xilinx

Examples loading text file or an image into FPGA and running on FPGA:

How to load a text file or an image in a testbench Verilog/ VHDL code for simulation:

- For Verilog testbench code: here
- For VHDL testbench code: here

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  1. Replies
    1. Thanks. Please keep update the blog:

  2. No problem. If you want to get FPGA Verilog VHDL projects for free, please come to this site to get detailed tutorials. Thanks

  3. I can't simulate? I failed "Index range 4 downto 0 is not compatible with index subtype (1 to 2147483647) of std.standard.string." at "generic (
    stim_file: string := "sim2.dat" ); "
    please help me?

    1. Please send me your full code and sim2.dat. I will help to debug.

    2. library ieee;
      use ieee.std_logic_1164.all;

      use std.textio.all;
      use work.txt_util.all;

      entity FILE_READ is
      generic (
      stim_file: string := "sim.txt"
      CLK : in std_logic;
      RST : in std_logic;
      Y : out std_logic_vector(4 downto 0);
      EOG : out std_logic
      end FILE_READ;

      architecture read_from_file of FILE_READ is
      file stimulus: TEXT open read_mode is stim_file;
      receive_data: process
      variable l: line;
      variable s: string(y'range);
      EOG <= '0';
      wait until RST='1';
      wait until RST='0';
      while not endfile(stimulus) loop
      readline(stimulus, l);
      read(l, s);
      Y <= to_std_logic_vector(s);
      wait until CLK = '1';
      end loop;
      print("I@FILE_READ: reached end of "& stim_file);
      EOG <= '1';
      end process receive_data;
      end read_from_file;

    3. mình lưu file sim.txt ở ổ đĩa c nó chứa các giá trị nhị phân 1 và 0 thôi.
      và mục đích của mình là mình muốn cứ mỗi xung clock thì mình đọc về 1 giá trị nhị phân từ 1 file .bin
      bạn có thể sửa lại code giúp mình với ?

    4. Hi Luc,
      Bữa giờ bận giờ mới reply bạn đc, bạn gửi file sim.txt và code qua email : rồi mình sẽ sửa code cho bạn nhé.

    5. mình có mail cho bạn rồi ha :)

    6. Check mail di ban. Minh gui cho ban 1 code testbench don gian read binary text file cua ban roi nhe.

  4. how to implement usb 2.0 protocol on fpga(spartan 3e evaluation board)

    1. You need to study how USB works and understand the specification of USB 2.0. Then you can design circuits to implement the protocol.

  5. where can i study how to implement and FPGA ALTERA.. i just wanna the base for start the implementation

  6. You can check some tutorial videos on Youtube and practice simple FPGA projects on

  7. how to convert the RGB image into gray scale image and then to binary image in verilog HDL

    1. For simplicity, just use this formula for converting RGB to Gray scale image:
      Gray = (R + G + B) / 3.
      Read binary image in Verilog, follow the following tutorial:


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